This applet is a fast and easy design tool for 3rd & 4th order Phase Locked Loops (PLL). It includes the following functions :

• calculation of the loop filter for achieving a desired frequency response.
• simulation of the PLL for a given user defined loop filter.
• calculation of the noise performance of the PLL, including the contribution of the quantization noise for a fractionnal-N PLL.
• simulation of the transient locking response.

The applet is similar to a spreadsheet. Data is entered in the editable cells. The input data consist of frequencies, division ratios, noise parameters, targeted cut-off frequency for the PLL or the description of the loop filter. The results of calculations are displayed in the non-editable cells, and in different graphs which show the AC response of the PLL, the SSB output phase noise and the transient locking response. The results are automatically updated when pressing the Enter key. Help on context can be obtained by clicking the headers of the cell group.

The PLL is a feedback circuit which lock the phase and the frequency of a Voltage Controlled Oscillator (VCO) to a reference oscillator, usually of high spectral purity. A PLL can have various applications but we consider here more particularly the application of PLLs to frequency synthesis, i.e. generation of a signal with a frequency which is a programmable multiple of the reference oscillator frequency.

The reference oscillator is the starting point of the PLL. Its frequency is usually divided to a lower frequency called comparison frequency, because this is the frequency at which the phase comparison is performed. The frequency divided reference signal is one input of the phase comparator. The other is obtained from a frequency division of the RF oscillator signal. When the PLL is locked, the two inputs of the phase comparator are at the same frequency. It results immediately that :

• fRef / m = fRF / n = fcomp

The phase detector is the key element of the PLL. Several types of phase detector are possible but we consider in this PLL model a phase-frequency detector with a charge pump as output circuit. This kind of detector is the most common in modern PLL. It is frequency sensitive, i.e. able to deliver an average current of the same polarity as the frequency error. This property ensures convergence towards the wanted frequency even if the initial frequency error is large. The charge pump output circuit of the detector delivers current pulses of constant amplitude but with duration proportional to the phase error.

The type of PLL you want to design and simulate, either an integral'N or fractionnal'N PLL, is the first choice which is requested in this spreadsheet. Then, you must specify the operating frequencies of the PLL :

• The frequency of the RF VCO, fRF ;
• The frequency of the reference oscillator, fRef ;
• The comparison frequency, fcomp.

The appropriate division ratios to get from fRF or fRef down to fcomp are automatically calculated.

The loop circuit, consisting of the phase detector, charge pump, filter, VCO and RF divider, has an open loop frequency response as indicated in the figure on the right. In design mode, the RC components of the filter are automatically determined from the unity gain frequency f0, i.e. the frequency at which the loop gain is 1 in linear, or 0 dB. The unity gain frequency of the PLL will be about of the same order of magnitude, but its exact value will depend on the parameter X called 'symetry ratio' . This parameter allows to control the position of the zero fz and of the high frequency pole(s) fp of the loop transfer function with respect to f0. The location of pole(s) and zero is determined by :

• f0 / fz = X
• fp / f0 = f(X), with f(X) = X for a second order filter.

Moving fz and fp closer to f0 decreases the phase margin. The PLL response exhibits a higher overshoot and can become unstable. Moving fz and fp apart from f0 improves the phase margin. The overshoot is reduced or disappears, the stability gets better. The optimum value of X is about 2.7 to 3 for achieving a good stability and the minimum locking time.

For a second order filter, there is only one high frequency pole at frequency fp. If a third order filter is selected, there are two high frequency poles. Their location with respect to the optimum pole frequency fp is determined by the parameter k according to :

• fp1 = (1-k)*fp
• fp2 = (1+k)*fp

In simulation mode, you specify the components of the filter. The applet calculates the unity gain frequency of the loop and the corresponding phase margin.

The open loop gain of the PLL is the product of the gains blocks in the loop. Therefore the gains of the phase detector and of the RF VCO must be specified to enable calculation of the appropriate loop filter.

The phase detector gain Kd is calculated from the sink/source current amplitude Ipeak. The gain relates the average current delivered over one period of the comparison frequency, to the phase difference of the input signals of the phase detector. For a conventional phase-frequency detector as assumed in the PLL model, the detector gain, in mA/radian, is given by :

• Kd = Ipeak / (2*pi)

The RF VCO gain Kvco specifies how fast the VCO frequency varies with the control voltage. A linear tuning characteristic is assumed for simplification. The VCO gain has the dimension of MHz/V.

The RF VCO phase noise is assumed to decrease by 30dB/decade close to the carrier, then by 20dB/decade until the noise floor is reached. The characteristic is specified by giving the corner frequencies and the corresponding phase noise. The 30dB corner frequency is the offset frequency at which the slope changes from 30 to 20dB/decade. The 20dB corner frequency is the offset frequency at which the noise floor is reached.

The phase noise of the reference path is assumed to decrease by 20dB/decade very close to the carrier, until the floor is reached. The characteristic is described by the corner frequency at which the noise floor is reached, and the corresponding phase noise. This model is used to represent not only the noise of the reference oscillator but includes also the contribution of the reference amplifier.

The phase noise of the dividers is referred to the comparison frequency.

The noise of the phase detector (PFD) is also referred to the comparison frequency. It does not include the noise of the charge pump which is treated separately. This is the noise of the flip-flop circuits implementing the phase-frequency detection function.

The noise current of the charge pump is an input parameter of the PLL noise model. It can be extracted from a Pnoise simulation in locked state conditions (zero average current over a period of comparison).

For calculation of the comparison frequency breakthrough (tone at distance equal to comparison frequency in the PLL output spectrum), a charge pump current waveform as indicated in the picture on the right is assumed. It accounts for practical limitations which make the occurence of very narrow up/down current pulses unavoidable. In the model, the zero average current waveform characterizing the locked state is modeled as two adjacent up/down pulses of equal areas, with duration Tau and height Ipeak. In case of DC leakage, the current pulse with opposite sign to the leakage current is extended in order to maintain a zero mean current. The comparison frequency breakthrough at PLL output is calculated by applying the loop filter and VCO transfer functions to the spectral component at comparison frequency contained in the charge-pump waveform.

The breakthrough is calculated in integral N mode only. For a fractional PLL, tones in the output spectrum are more difficult to calculate analytically. Their level and position depends on the fractional division ratio and on the statistics on the divider modulation signal. Therefore no calculation of output tones is done for a fractional PLL in this tool.

There are 3 graphs which can be displayed, but one at a time, using the choice bar. The graphs are the following :

• PLL gain : this graph displays the phase response of the PLL at the output of the RF VCO, using a linearized model of the PLL.
• PLL noise and its contributions : using the noise parameters of the PLL building blocks entered by the user, the SSB phase noise at the VCO output is computed using the above mentionned linear model of the PLL.
• PLL locking (response to a frequency jump) : the model assumes a pulse width modulated error signal. This is more accurate than continuous time and sampled linear models generally assumed, yet not fully exact since the error pulse is modulated both in width and position in a real PLL. The difference is depicted by the figure on right. In the model, the pulse always starts at the beginning of a comparison period, whereas it can start earlier in an actual PLL when the feedback signal is in advance.